Along with the rapid progress in miniaturization and higher performance of electronic systems, development of three-dimensional semiconductor integrated circuit devices is being accelerated. As a typical approach to a three-dimensional technology, there is a chip stacking technology using through electrodes. In the case where a silicon substrate is used, the through electrodes are also referred to as TSV (through silicon vias). Such a three-dimensional technology is disclosed in Japanese Patent Application Publication No. 2004-47938.
With the three-dimensional technology, substrates are bonded via bumps, and then through electrodes and the bumps are bonded. For this reason, accurate alignment between the substrates in the bonding process cannot be performed, and thus there is a problem in that the through electrodes cannot be formed in high density. In addition, there is a problem in that the parasitic capacitance around the through electrodes is large, and thus wiring delay occurs. In the case where a through electrode is used for a signal line as a transmission line, longer line length and larger parasitic capacitance cause the power consumption of an integrated circuit to increase, and thus makes high-speed transmission difficult.